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may 2015 docid027902 rev 1 1 / 13 this is information on a product in full production. www.st.com STP12N60M2 n - channel 600 v, 0. 395 typ., 9 a mdmesh? m2 power mosfet in a to -220 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STP12N60M2 600 v 0. 450 9 a 85 w ? extremely low gate charge ? excellent output capacitance (c oss ) profile ? 100% avalanche tested ? zener - protected applications ? switching applications description this device is an n - channel power mosfet developed using mdmesh? m2 technology. thanks to its strip layout and an improved vertical structure, the device exhibits low on - resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. table 1: device summary order code marking package packing STP12N60M2 12n60m2 to -220 tube
contents STP12N60M2 2 / 13 docid027902 rev 1 contents 1 electrical ratings ............................................................................. 3 2 electrical characteristics ................................................................ 4 2.1 electrical characteristics (curves) ...................................................... 6 3 test circuits ..................................................................................... 8 4 package information ....................................................................... 9 4.1 to - 220 type a package information ................................................ 10 5 revision hist ory ............................................................................ 12
STP12N60M2 electrical ratings docid027902 rev 1 3 / 13 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d drain current (continuous) at t case = 25 c 9 a drain current (continuous) at t case = 100 c 5.7 i dm (1) drain current (pulsed) 36 a p tot total dissipation at t case = 25 c 85 w dv/dt (2) peak diode recovery voltage slope 15 v/ns dv/dt (3) mosfet dv/dt ruggedness 50 t stg storage temperature - 55 to 150 c t j operating junction temperature notes: (1) pulse width is limited by safe operating area. (2) i sd 9 a, di/dt=400 a/s; v ds (peak) < v (br)dss , v dd = 80% v (br)dss . (3) v ds 480 v. table 3: thermal data symbol parameter value unit r thj -case thermal resistance junction - case 1.47 c/w r thj - amb thermal resistance junction - ambient 62.5 table 4: avalanche characteristics symbol parameter value unit i ar (1) avalanche current, repetitive or not repetitive 2.6 a e ar (2) single pulse avalanche energy 117 mj notes: (1) pulse width limited by t jmax . (2) starting t j = 25 c, i d = i ar , v dd = 50 v.
electrical characteristics STP12N60M2 4 / 13 docid027902 rev 1 2 electrical characteristics (t case = 25 c unless otherwise specified) table 5: static symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 600 v i dss zero gate voltage drain current v gs = 0 v, v ds = 600 v 1 a v gs = 0 v, v ds = 600 v, t case = 125 c 100 i gss gate - body leakage current v ds = 0 v, v gs = 25 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain - source on- resistance v gs = 10 v, i d = 4.5 a 0.395 0.450 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 538 - pf c oss output capacitance - 29 - c rss reverse transfer capacitance - 1.1 - c oss eq. (1) equivalent output capacitance v ds = 0 to 480 v, v gs = 0 v - 106 - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 7 - q g total gate charge v dd = 400 v, i d = 9 a, v gs = 10 v (see figure 15: "gate charge test circuit" ) - 16 - nc q gs gate - source charge - 2.3 - q gd gate - drain charge - 8.5 - notes: (1) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 300 v, i d = 4.5 a r g = 4.7 , v gs = 10 v (see figure 14: "switching times test circuit for resistive load" and figure 19: "switching time waveform" ) - 9.2 - ns t r rise time - 9.2 - t d(off) turn - off delay time - 56 - t f fall time - 18 -
STP12N60M2 electrical characteristics docid027902 rev 1 5 / 13 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source- drain current - 9 a i sdm (1) source- drain current (pulsed) - 36 a v sd (2) forward on voltage v gs = 0 v, i sd = 9 a - 1.6 v t rr reverse recovery time i sd = 9 a, di/dt = 100 a/s, v dd = 60 v (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 284 ns q rr reverse recovery charge - 2.4 c i rrm reverse recovery current - 17 a t rr reverse recovery time i sd = 9 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 404 ns q rr reverse recovery charge - 3.5 c i rrm reverse recovery current - 17.5 a notes: (1) pulse width is limited by safe operating area. (2) pulse test: pulse duration = 300 s, duty cycle 1.5%.
electrical characteristics STP12N60M2 6 / 13 docid027902 rev 1 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STP12N60M2 electrical characteristics docid027902 rev 1 7 / 13 figure 8 : capacitance variations figure 9 : normalized gate thresho ld voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : output capacitance stored energy figure 13 : source - drain diode forward characteristics t j (c) i d = 250 a v gs(th) 1.00 0.90 0.80 0.70 -50 0 (norm) 1.10 50 100 am03184v1 gipg290120151002als 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 4 8 12 16 v sd (v) t j = -50 c t j = -25 c t j = 150 c i sd (a)
test circuits STP12N60M2 8 / 13 docid027902 rev 1 3 test circuits figure 14 : switching times test circuit for resistive load figure 15 : gate charge test circuit figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load tes t circuit figure 18 : unclamped inductive waveform figure 19 : switching time waveform
STP12N60M2 package information docid027902 rev 1 9 / 13 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information STP12N60M2 10 / 13 docid027902 rev 1 4.1 to - 220 type a package information figure 20 : to - 220 type a package outline
STP12N60M2 package information docid027902 rev 1 11 / 13 table 9: to - 220 type a mechanical data dim. mm min. typ. max. a 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 d 15.25 15.75 d1 1.27 e 10 10.40 e 2.40 2.70 e1 4.95 5.15 f 1.23 1.32 h1 6.20 6.60 j1 2.40 2.72 l 13 14 l1 3.50 3.93 l20 16.40 l30 28.90 ?p 3.75 3.85 q 2.65 2.95
revision history STP12N60M2 12 / 13 docid027902 rev 1 5 revision history table 10: document revision history date revision changes 22- may -2015 1 first release.
STP12N60M2 d ocid027902 rev 1 13 / 13 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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